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as8520 lin transceiver with voltage regulator, attenuator, relay drivers, mcu interface for automotive applications www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 1 - 34 preliminary data sheet 1 general description the as8520 is a companion ic for sensor and actuator lin slaves. the device provides application specific add-ons, such as the resistive attenuator for battery voltage sensing, a micro controller interface to control 2 relay drivers, to access control register, and diagnosis options. the as8520 has a window watchdog which can be enabled as a factory option. 2 key features operating voltage 6 to 18v, max. 42v for 500 ms linear, low-drop voltage regulator: v cc = 5v 3% or v cc = 3.3v as a factory option 50ma load current typical 35 a quiescent current in standby mode undervoltage detection with reset output, factory adjustable undervoltage threshold and reset time lin bus transceiver with load independent slew control con- forming to lin 2.0 a nd sae j2602, short circ uit protection, tx time out fail safe feature, over temperature warning and shut down micro controller 4-wire interface for relay driver control, device configuration, status and diagnosis read out, register read / write operating modes: normal and standby or normal and sleep as a factory option window watchdog with timing options if factory enabled backup registers to store mcu data during v cc shut down voltage attenuator with disable. factory selectable ratio options of 21 and 481 two low side relay drivers r on < 5 -40oc to +125oc ambient operating temperature aec q 100 automotive qualified 6kv esd on lin pin according to iec 61000-4-2 24bit chip id for traceability and module id 24-pin qfn (6x6) package 3 applications the as8520 is suitable for small actuator or sensor lin slaves. the device is ideal for lin 2.0/2.1 network applications like window lift actuators, sunroof actuators, seat actuators and battery sensors. figure 1. as8520 lin transceiver block diagram vsup en vcc mode control temperature limiter reset block tshd reset bus 30k rx receiver vsup vcc tx transmitter vss por- vsup reset_vsup_n vbat_div vbat ldrive1 ldrive2 cs sclk sdo sdi spi interface, diagnostic, window watchdog (wwd) vcc vcc ldo por- vcc slew control lin wakeup control signals lin transceiver relay driver resistive divider reset_vsup_n reset_vcc_n wwd output gnd gnd vss as8520
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 2 - 34 as8520 preliminary data sheet - contents contents 1 general description............................................................................................................ ........................................................ 1 2 key features ................................................................................................................... ............................................................ 1 3 applications ................................................................................................................... ............................................................. 1 4 pin assignments................................................................................................................ ......................................................... 4 4.1 pin descriptions.......................................................................................................... .............................................................................. 4 5 absolute maximum ratings....................................................................................................... ................................................ 6 6 electrical characteristics..................................................................................................... ...................................................... 7 6.1 detailed system and block specifications .................................................................................. ............................................................. 8 6.1.1 low dropout regulator................................................................................................... .............................................................. 8 6.1.2 lin transceiver ......................................................................................................... ................................................................... 9 6.1.3 v cc undervoltage reset and window watchdog........................................................................................ .............................. 11 7 detailed description ........................................................................................................... ...................................................... 14 7.1 block description......................................................................................................... ........................................................................... 14 7.1.1 voltage regulator (ldo) ................................................................................................. ........................................................... 14 7.1.2 temperature limiter ..................................................................................................... .............................................................. 14 7.1.3 vsup undervoltage reset ................................................................................................. ........................................................ 14 7.1.4 reset................................................................................................................... ..................................................................... 14 7.1.5 v cc undervoltage reset............................................................................................................ ................................................ 15 7.1.6 window watchdog (wwd) ................................................................................................... ...................................................... 15 7.1.7 resistive divider ....................................................................................................... .................................................................. 16 7.1.8 hv low side relay driver switches....................................................................................... .................................................... 16 7.1.9 lin transceiver ......................................................................................................... ................................................................. 16 7.2 operating modes and states................................................................................................ .................................................................. 16 7.2.1 normal mode ............................................................................................................. ................................................................. 16 7.2.2 standby mode............................................................................................................ ................................................................. 17 7.2.3 sleep mode.............................................................................................................. ................................................................... 17 7.2.4 temporary shutdown mode ................................................................................................. ...................................................... 17 7.2.5 thermal shutdown state .................................................................................................. .......................................................... 17 7.3 state diagram............................................................................................................. ............................................................................ 19 8 application information........................................................................................................ .................................................... 20 8.1 initialization............................................................................................................ ................................................................................. 20 8.2 wake-up................................................................................................................... .............................................................................. 21 8.3 over-temperature shutdown ................................................................................................. ................................................................ 21 8.4 lin bus transceiver ....................................................................................................... ....................................................................... 21 8.4.1 transmit mode........................................................................................................... ................................................................. 21 8.4.2 receive mode............................................................................................................ ................................................................. 21 8.5 rx and tx interface ....................................................................................................... ........................................................................ 22 8.5.1 input tx ................................................................................................................ ...................................................................... 22 8.5.2 output rx ............................................................................................................... .................................................................... 22 8.6 mode input en............................................................................................................. ......................................................................... 23 8.7 serial port interface..................................................................................................... ........................................................................... 25 8.7.1 device configuration using 4-wire serial port ........................................................................... ................................................ 25 8.8 control and diagnosis registers ........................................................................................... ................................................................. 29 8.8.1 definition of control and status registers.............................................................................. .................................................... 29 8.9 esd/emc remarks ........................................................................................................... ................................................................. 31
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 3 - 34 as8520 preliminary data sheet - contents 8.9.1 general remarks......................................................................................................... ............................................................... 31 8.9.2 esd-test ................................................................................................................ .................................................................... 31 8.9.3 emc..................................................................................................................... ...................................................................... 31 9 package drawings and markings.................................................................................................. .......................................... 32 10 ordering information........................................................................................................... ................................................... 34
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 4 - 34 as8520 preliminary data sheet - pin assignments 4 pin assignments figure 2. pin assignments (top view) 4.1 pin description s table 1. pin descriptions pin name pin number description vsup 1 positive power supply lin 2 lin bus vss 3 gnd vbat_div 4 attenuated battery voltage vbat 5 battery voltage sensing line ldrive1 6 low side driver ldrive2 7 low side driver nc 8 not connected. nc 9 not connected. nc 10 not connected. nc 11 not connected. sdi 12 serial data in sclk 13 serial clock sdo 14 serial data out cs 15 chip select for serial interface rx 16 lin transceiver receive signal tx 17 lin transceiver transmit signal reset 18 digital output referenced to v cc , active low vbat_div lin en vsup vss vbat ldrive1 vcc rx reset sdo cs ldrive 2 as8520 tx 24 pin qfn-24 sclk sdi vss 24 23 22 21 20 19 7 8 9 10 11 12 18 17 16 15 14 13 1 2 3 4 5 6
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 5 - 34 as8520 preliminary data sheet - pin assignments v cc 19 regulated 5v/3.3v supply for loads up to 50ma, otp selectable (factory programmable) vss 20 gnd nc 21 not connected. nc 22 not connected. nc 23 not connected. en 24 high voltage compatible. enable pin with pull down to vss, active high. table 1. pin descriptions pin name pin number description
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 6 - 34 as8520 preliminary data sheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in section 6 electrical characteristics on page 7 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments dc supply voltage vsup -0.3 18 v 42 transient up to 500ms duration en -0.3 vsup + 0.3 v v cc -0.3 7 v lin -27 +40 v vbat -27 +42 v ldrive1, ldrive2 -0.3 50 v reset, rx, tx, cs, sclk, sdo, sdi, vbat_div -0.3 v cc + 0.3 v input current (latchup immunity) i scr -100 100 ma norm: jedec 78 electrostatic discharge (esd) 2 kv for on board signals v cc , tx, rx, reset, cs, sclk, sdo, sdi, vbat_div, en 4 for vbat, vsup, vss, ldrive1, ldrive2 8 lin to gnd, hbm model 6 lin to gnd, iec6100-4-2 0.5 lin to gnd, cdm 0.1 lin to gnd, mm total operating power dissipation (all supplies and outputs) p t 0.75 w qfn 24 in still air, soldered on jedec standard board @125o ambient, static operation = no time limit thermal package resistance (r th ) 33 k/w soldered on jedec standard board @125o ambient, static operation = no time limit storage temperature (t strg ) -55 +150 oc package body temperature (t body ) +260 oc the reflow peak soldering temperature (body temperature) is specified according ipc/jedec j- std-020c ?moisture/reflow sensitivity classification for non hermetic solid state surface mount devices?. humidity non-condensing 5 85 %
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 7 - 34 as8520 preliminary data sheet - electrical characteristics 6 electrical characteristics table 3. electrical characteristics symbol parameter conditions min typ max units operating conditions vsup positive supply voltage normal operating condition 6 18 v jump-start/ over-voltage condition 27 v load dump condition 42 v vss negative supply voltage 0 v t amb ambient temperature max junction temperature (t j ) 150oc -40 +125 oc i supp supply current 65 ma dc/ac characteristics for digital inputs and outputs 1 1. all pull-up, pull-downs are implemented with active devices. reset, rx, sd o have been measur ed with 10pf load. enable input v ih high level input voltage 0.8v cc v v il low level input voltage 0.2v cc v i leak input leakage current en = l -1 +1 a i pd_en pull down current en = v cc = 5v 30 100 a tx, cs input v ih high level input voltage 0.8v cc v v il low level input voltage 0.2v cc v i leak input leakage current tx = v cc -1 +1 a i pu pull up current rx, tx,cs pulled to v cc -100 -30 a sdi, sclk v ih high level input voltage 0.8v cc v v il low level input voltage 0.2v cc v i leak input leakage current -1 +1 a i pd_spi pull down current sdi, sclk pulled to vss 30 100 a reset, sdo v oh high level output voltage vsup 6v, i = 1 ma v cc -0.5 v v ol low level output voltage vsup 6v, i = 1 ma vss + 0.4 v rx v oh high level output voltage vsup 6v, i = 1 ma v cc -0.5 v v ol low level output voltage vsup 6v, i = 1 ma vss + 0.4 v i pu_reset pull-up current pulled up to v cc -100 -30 a
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 8 - 34 as8520 preliminary data sheet - electrical characteristics 6.1 detailed system and block specifications 6.1.1 low dropout regulator the ldo is a linear voltage regulator, which provides a regulated (band-gap stabilized) output voltage (v cc ) from the battery supply voltage (vsup). (6v < vsup < 18v; -40oc < t j < +150oc; all voltages are with respect to ground (vss); positive current flows into the pin), norm al operating mode if not otherwise mentioned. table 4. system specifications symbol parameter conditions min typ max units idd nom current consumption normal mode no load on v cc , lin inactive, vsup = 14v, res_div enabled 300 a no load on v cc , lin active, vsup = 14v, res_div enabled 700 no load on v cc , lin inactive, vsup = 14v, res_div disabled 250 idd stby current consumption standby mode @ 85oc ambient (no load) 40 a @125oc ambient (no load) 45 idd sleep current consumption sleep mode @ 85oc ambient (no load) 30 a @ 125oc ambient (no load) 35 table 5. ldo block specifications symbol parameter conditions min typ max units vsup battery voltage range default, need safe operating area calculations with package rth 61218v v cc output voltage range load < 50ma 4.85 5.0 5.15 v factory option, load < 50ma 3.15 3.3 3.45 50 to 65ma 4.5 5.15 factory option, 50 to 65ma 2.9 3.3 3.45 standby mode @ icc < 5ma 4.5 5.5 load-dump condition, iload < 50ma 5.5 factory option, standby mode @ icc < 5ma 33.6 icc_sh output short circuit current normal mode 50 250 ma standby mode 5 250 dv cc 1 line regulation v cc / vsup 8 mv/v loreg_sm load regulation (standby mode) v cc / iccn (for iload > 500ua) 10 mv/ma loreg_nm load regulation (normal mode) v cc / iccn (for iload > 500ua) 1 mv/ma cl1 output capacitor (electrolytic) 2.2 10 f esr1 110 cl2 output capacitor (ceramic) 100 220 nf esr2 0.02 1 csup1e input capacitor (electrolytic) for emc suppression 10 100 f esr1_csup 110 csup2c input capacitor (ceramic) for emc suppression 100 220 nf esr2_csup 0.02 1
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 9 - 34 as8520 preliminary data sheet - electrical characteristics 6.1.2 lin transceiver (4.5v < v cc < 5.5v; 6v < vsup < 18v; -40oc < t j < 150oc, vbus is the voltage on the lin node. all voltages are with respect to ground (vss); positive current flows into the pin. table 6. dc electrical characteristics symbol parameter conditions min typ max units driver i bus_lim current limitation in dominant state lin = vsup_max 40 120 200 ma lin_v ol output voltage bus (dominant state), i lin = 40ma (short-circuit condition tested at v ol = 2.5v) 2v pull-up resistor normal mode (recessive bus level on tx pin) 20 40 60 k i bus_leak_rec driver off; vsup = 7.3v, 8v www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 10 - 34 as8520 preliminary data sheet - electrical characteristics d4 (worst case 10.4kbps transmission) v th_rec (min) = 0.389 x v sup ; v th_d om (min) = 0.251 x v sup ; v sup = 6v...18v; t bit = 96 s; d4 = tb us_rec(max) / (2 x t bit ) otp selection = low slew mode 0.59 t dlr v cc = 5v; propagation delay bus dominant to rx low 6s t dhr v cc = 5v; propagation delay bus dominant to rx high 6s t rs receiver delay symmetry -2 2 s t wake wake-up delay time 30 150 s t sln transition from standby mode to normal mode (clock frequency is 128khz 25%) 4 clock cycles t nsl transition from normal mode to standby mode (clock frequency is 128khz 25%) 6 clock cycles t rec_deb receiver de-bounce time 0.6 1 s c int internal capacitance of the lin node configured as a slave 250 pf table 8. temperature limiter symbol parameter conditions min typ max units t sd shut down temperature junction temperature 144 176 oc t ret return temperature 1 2 126 154 oc t otset over-temp warning flag set the temperature beyond which the warning flag is set. 126 154 oc t otclear over-temp warning flag clear the return temperature when the warning flag is cleared 108 132 oc 1. during shut down, the sensor must be powered by vsup. 2. thermal shut down disables ldo and sets all drivers to high impedance, the ic returns from shut down with por table 9. tx timeout watchdog symbol parameter conditions min typ max units t lin_wdog time out duration (dominant state) 0.5 1 2 s table 7. ac electrical characteristics symbol parameter conditions min typ max units
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 11 - 34 as8520 preliminary data sheet - electrical characteristics figure 3. lin timing diagram 6.1.3 v cc undervoltage reset and window watchdog the values in this table are valid for normal and standby modes. all parameters are tested unless mentioned. table 10. electrical characteristics symbol parameter conditions min typ max units vuvr_off v cc under-voltage threshold off rising edge of v cc 2.55 2.95 v vuvr_on v cc under voltage threshold on falling edge of v cc 2.3 2.7 v vuvr1_off v cc under voltage threshold off (default) rising edge of v cc 3.0 3.4 v vuvr1_on v cc under voltage threshold on (factory option) falling edge of v cc 2.75 3.15 v vuvr2_off v cc under voltage threshold off (factory option) rising edge of v cc 3.5 3.9 v vuvr2_on v cc under voltage threshold on (factory option) falling edge of v cc 3.25 3.65 v vuvr3_off v cc under-voltage threshold off (factory option) rising edge of v cc 4.0 4.4 v vuvr3_on v cc under voltage threshold on (factory option) falling edge of v cc 3.75 4.15 v vhyst_vcc hysteresis of under-voltage threshold on/off v cc default and all other otp options 0.1 0.25 0.4 v t rr spike filter on v cc to remove disturbance 4 s vsuvr_off vsup under-voltage threshold off 3.85 v vsuvr_on vsup under-voltage threshold on bor level (considered to be the master reset for as8520) 3.25 v hysteresis on under-voltage threshold on/off vsup 0.2 0.5 0.7 v wd_tcl wwd non-service time (if factory enabled) reset will be generated 1 0-75 0 -100 0-125 ms wd_tsv wwd service ? time (if factory enabled) reset will not be genera ted 75-150 100-200 125-250 ms vth_rec(max) vth_dom(max) vth_rec(min) vth_dom(min) t bus_dom(max) t bus_rec(min) t bus_dom(min) t bus_rec(max) txd t bit t bit lin
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 12 - 34 as8520 preliminary data sheet - electrical characteristics t res reset delay time 4ms, 16ms, 32ms (typ) are factory options (min = -25% and max = +50% of typical) 6812ms t shd temporary shutdown reset active time 0.1 1 s 1. -40%, -20%, +20%, +60%, and +100% timings are available as factory options. table 11. resistive divider symbol parameter conditions min typ max units r rhrl division ratio 1 20.8 21 21.2 vin_bat input battery voltage range ldo must turn on 6.8 18 v v bat_leak v bat = 18v -1 1 a tc rhrl temperature drift of dividing ratio from -40 to +125 deg (guaranteed by design) 11v www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 13 - 34 as8520 preliminary data sheet - electrical characteristics timing parameters when entering 4-wire spi mode (for determination of clk polarity) t cps clock setup time (clk polarity) setup time of sclk with respect to cs falling edge 20 ns t cphd clock hold time (clk polarity) hold time of sclk with respect to cs falling edge 20 ns table 13. spi interface symbol parameter conditions min typ max units
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 14 - 34 as8520 preliminary data sheet - detailed description 7 detailed description the as8520 chip consists of a low drop-out regulator 5v/50ma, two low-side relay drivers, a resistive divider to monitor batter y voltage and a lin bus transceiver, which is a bi-directional bus interface for dat a transfer between lin bus and the lin protocol controller. add itionally integrated is a reset unit with a power-on-reset delay a nd a programmable watch dog time. it also includes a wa tchdog time-out on lin tx node to indicate if the microcontroller is stuck in a loop and the lin bus remains in dominant time for more than the necessary time. 7.1 block description the main blocks of the as8520 are explained below. 7.1.1 voltage regulator (ldo) the voltage regulator has three operating modes. the features of the operating modes are given below: normal mode: stability to be better 0.15v over input range and temperature for load current up to 50ma. the ldo output provides a volt- age of 5v (3.3v as otp option). standby mode: the standby mode is a low quiescent current mode used in car applications that are always switched on. the load current in standby mode is 5ma. quiescent current (no load) is less than 25a typically at room temperature. power down mode: the power down or temporary shutdown of the regulator can be set by a register bit. this bit can be written through 4- wire mcu interface. the ldo takes the input from bandgap and scales it up to the r equired voltage. the ldo starts charging only after the por-vsup event occurs (reset_vsup_n switched from low to high). the ldo can be powered- down by a control signal (temporary shutdown register) for the temporary shutdown mode. 7.1.2 temperature limiter temperature limiter produces a power down when temperature exceed s 160oc 10%. it powers up and generates a reset when it retur ns to 140oc 10% junction temperature. during thermal shut down, temperature sensor is supplied by vsup. there is an option control b it provided to enable or disable this temperature monitoring circuit. during the temperature ramp-up phase, as soon as the temperature exceeds 140oc 10%, a warning signal is issued and is written into the diagnostic register, which can be read through the spi interface. 7.1.3 vsup undervoltage reset vsup undervoltage reset generates a reset reset_vsup_n, swit ched from low to high when vsup ramps up above vsuvr_off. this is used to enable proper initialization of mode control and diagnosti c registers. if vsup < vsuvr_on, then reset_vsup_n switches f rom high level to low level (active). this is considered to be the master reset and will have the highest priority over all other signal s. as soon as vsup < vsuvr_on, the ldo, lin transceiver is completely shut off and system comes to a complete stop. as8520 enters into the normal op erating mode only after vsup > vsuvr_off. 7.1.3.1 vsup undervoltage in normal mode supply voltages below vsuvr_off and above vsuvr_on do not influence the voltage regulator. the output voltage v cc follows vsup. 7.1.3.2 vsup undervoltage in standby mode / sleep mode no exit from the sleep mode or standby mode take place if th e vsup voltage drops down to vsu vr_off. if vsup goes below vsuvr_on , reset_vsup_n is active and resets the mode control and diagnosti c register. the voltage regulator, lin transceiver modules are turned off. if vsup rises again above vsuvr_off, reset_vsup_n is switched from low to high. the syst em enters normal mode where lin transceive r and ldo are switched on. 7.1.3.3 vsup undervoltage in low slew mode the behavior of as8520 at low vsup voltages is equal to the sleep mode. the low slew mode (set by control register through seri al interface as an option) will be cancelled, if vsup drops below vsuvr_on in this mode. the as8520 enters the normal mode, if vsup rises again above vsuvr_off. 7.1.4 reset reset generates an external reset signal to reset the microcontroller a nd all other exter nal circuits. the reset functionality is illustrated in figure 4 . reset consists of a digi tal buffer at the output. reset sign al can be affected by reset_vcc_n (which is the u nder-voltage res et on v cc ) and window watchdog output. all those conditions which cause a drop in the v cc voltage will be detected from the low voltage reset unit, which in-turn generates a reset signal. states like temporary shut-down, over-temperature monitor will influence the reset outp ut through reset_vcc_n signal only.
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 15 - 34 as8520 preliminary data sheet - detailed description figure 4. reset functionality 7.1.5 v cc undervoltage reset the por-vcc generates reset_vcc_n signal as output which determines under-voltage reset of the output of the ldo. the rising ed ge of the v cc gives an under-voltage reset ?off? and the falling edge of the v cc gives an under-voltage reset ?on?. this under-voltage signal is used to control the reset output. when v cc rises up vuvr_off for a period greater than reset duration (tres) then reset_vcc_n switches from low level to high level and pin r eset is inactive (high). if v cc falls below vuvr_on for a period grea ter than a predetermined delay (trr) then reset_vcc_n switches from high level to low level an d pin reset is active (low). the rese t_vcc_n signal is us ed to initialize w indow watchdog timer, tx time-out, test control circuits, 4-wire spi, and logic associated with spi (everything other than the spi co ntrol registers). v cc under-voltage reset threshold voltage level adjustment can be made by 2 bit otp as explained in otp interface. 7.1.6 window watchdog (wwd) to keep the external microcontroller always in proper function state, a window watchdog circuit is implemented. the wwd trigger is generated by external mcu through spi interface. if the window is missed, a reset on the reset pin with certain reset time (t res ) is generated. the wwd function can be e nabled or disabled by fact ory setting. the watchdog is started after the assp exits reset. under normal workin g conditions, microcontroller gives a wwd trigger every time in the window peri od of wd_tsv (service time). if the trigger does not occur dur ing wd_tsv or occurs too early during wd_tcl (n on-service time), then reset ou tput is pulled low (active), wh ich will reset the micro-control ler. wwd circuit is turned on after the reset pin goe s back to high (inactive). if v cc < vuvr_on, wwd circuit is switched off. when the wwd function is enabled, there is a 3-bit factory programming available to set the trigger window. vcc vsup vuvr_of f t res t rr t>tj t www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 16 - 34 as8520 preliminary data sheet - detailed description figure 5. window watchdog trigger 7.1.7 resistive divider the resistive divider acts as a battery voltage attenuator. the output of this resistive divider can be connected to an adc for monitoring the battery voltage. the division ratio of resistive divider is 21 but can be set also to 481 as a factory programming option. both divider options can be disabled in standby mode using the en signal. reverse polarity protection of vbat pin is provided. 7.1.8 hv low side relay driver switches two nmos open drain relay driver devices provide over voltage prot ection. the driver is disabled if the mcu software hangs up ( watchdog reset or time out wd for lin tx). the input to the drivers is given through spi (low-side driver data register). if over voltage occu rs, the relay driver turns off irrespective of the input. the driver stays turned off till the voltage returns back to the normal operating range. a n optional control bit available in the device configuration register, which can be us ed to switch off the drivers independently to save power. the re lay drivers are disabled using the spi. 7.1.9 lin transceiver the transceiver provides short circuit limitation, hardware watchdog and over temperature shut down features. the tx watchdog t imer is active when tx is pulled low (active). as soon as the tx watchdog timeout occurs, the lin bus is released from dominant state to reces sive state. the lin transceiver has a pull-up resistor (for the slave node; extra resistor externally for the master node) to the vsup. a diode protection is available to protect it from back supply from bus line. the lin transmitter has the basic functionality of relaying the data from the micro-controller on to the lin. the data on the l in needs to have controlled slew to have reduced emi. the receiver relays the data from the lin to the micro-controller. this transmitter has op timized emc performance across different loading conditions conforming to the lin 2.1 standards. the wake-up detects a wake up event on the lin. 7.2 operating modes and states the as8520 provides four main operating modes ?normal?, ?sleep /stand-by? (programmed by otp), ?temporary shutdown? and ?thermal shutdown?. the lin transceiver can be programmed to operate with lower slew in the normal mode. refer to table 14 for a detailed description on transition for each mode. 7.2.1 normal mode this is the mode after the power-up. in normal mode, ldo, lin transceiver, window watchdog, resistive divider and the line driv ers are all turned on. all the blocks are completely functional. ldo is now capable of delivering maximum load current possible as per the device specifications. the lin transceiver is capable of sending the tx data from microcontroller to the lin bus at a maximum rate of 20kbps. resistive divider is used to attenuate the battery voltage and relay drivers are used to drive the relay. en signal is set to h igh and lin, tx, rx pins can be driven into dominant (low) or recessive (high) states. if the junction temperature increases more than t otset , a warning flag is set in the diagnostic register, which can be read through the spi interface. period non-service time (wd_tcl) service time (wd_tsv) trigger restart period trigger via spi last trigger point earliest possible trigger point (system will not reset) latest possible trigger point (system wil not be reset) 50 % 100 % valid trigger point (system will not be reset) unwanted trigger point (system will be reset)
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 17 - 34 as8520 preliminary data sheet - detailed description 7.2.2 standby mode standby mode is a functional low-power mode where the ldo is switched into a low-power state with low drive capability and lowe r accuracy of the output voltage. lin transceiver is disabled. the lin wake-up circuit and over-temperature monitor circuit is enabled. windo w watchdog, tx timeout watchdog, resistive divider, relay driver circuits are disabled. en pin held low in this mode. tx pin is in recessive s tate (high). cs is pulled to v cc while sdi and sclk ou tputs are pulled to vss. 7.2.3 sleep mode as a factory programming option on request the as8520 offers as a replacement to the standby mode with sleep mode. sleep mode i s the most current saving mode. if en is held low, the ldo, lin transceiver, the gate drivers, the resistive divider and the reset and win dow watchdog unit will be switched off. v cc is pulled down to zero. cs is low. the lin wake-up circuit, oscillator and over-temperature monitor circuit is active. lin bus is in recessive state (high). only wake-up possible is through remote wake-up, through lin pin, pulling it to dominant stat e for 100s typical (low), can change the state of the system. 7.2.4 temporary shutdown mode in this mode, the v cc is pulled down and the ldo is powered down. this mode is introduced to interface with other components which do not have a pin for the reset functionality. this provides an alternative way to reset those components interfacing with as8520. thi s mode is default disabled but can be enabled by an otp option. in this mode, all internal modules supplied by the ldo are disabled. only the osc illator, control registers are enabled. the v cc output can be temporarily switched off and pulled to vss. en signal, rx, tx is pulled low and lin transceiver along with the lin wake-up circuit is powered down. no remote wake-up functionality is possible. lin bus enters into recessive state. the system goes out of this mode to normal mode after the time-out of an internal counter delay (t shd ). normal mode to temporary shutdown transition will be controller by register bit in configuration register. 7.2.5 thermal shutdown state if the junction temperature t j is higher than t sd , the as8520 will be switched into the thermal shutdown mode. the transceiver is completely disabled. no wake-up functionality is available. window watchdog, tx timeout watchdog and ldo are completely turned off. only t he over- temperature monitor would be working. as soon as the temperature returns back to t ret , the system enters normal mode. for more information on transition, see table 14 . table 14. transition table transition interface reg. 0x05 d0 flags from mode to mode lin rx tx en rwake uvbat ot uvcc comments normal mode stand-by x-rs x-h 2 h 3 h-l 3 l x x inactive inactive tx is high for t stndy_triggerr sleep 1 x-rs x-h 2 h 3 h-l 3 l x x inactive set tx is high for t stndy_triggerr 1 temporary shutdown x-rs x-h 2 x h 3 h x x inactive set the control bit is set through the 4-wire spi interface over- temperature x-rs x-h 2 xxlxx set set temperature monitor output asserted (covered by scan) stand-by mode normal (lw) x h-x 2 x l-h 3 l x x inactive inactive normal (rw) x h-x 2 h x l set x inactive inactive remote wake up event occurred on lin temporary shutdown rs h 2 hl h 3 xxinactiveset the control bit is set through the 4-wire spi interface over- temperature rs h 2 hllxx set set temperature monitor output asserted (covered by scan)
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 18 - 34 as8520 preliminary data sheet - detailed description note: l = low state, h = high state, ot = over-temperature reset, uvcc = undervoltage v cc , uvbat = undervoltage vbat, rwake =remote wake, x = don?t care. temporary shutdown mode normal rs-x h-x 2 x x l x x inactive clear internal 128ms timer expired over- temperature mode normal rs-x h-x 2 x x l x x clear clear temperature monitor output de-asserted (covered by scan) sleep mode 3 normal rs-x h-x 2 x x l set x inactive clear remote wake up event occurred on lin over- temperature rs h 2 x x l x x set hold temperature monitor output asserted (covered by scan) all statespower offxxxxxx l-h 3 xx 1. chosen by factory programming option 2. effect of transition 3. cause for transition table 14. transition table transition interface reg. 0x05 d0 flags from mode to mode lin rx tx en rwake uvbat ot uvcc comments
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 19 - 34 as8520 preliminary data sheet - detailed description 7.3 state diagram the complete functional state machine for as8520 is illustrated in figure 6 . some soft-states in the fsm like ?txwd wait?, ?standby wait? and other ?wait? states have been included for the sake of completeness. figure 6. finite state machine model for the as8520 system reset timeout otp load init0 normal wait_test wait_otp ovtemp temp shut sleep standby por_vsup otp_load rx=0 test_en te mp s h ut dow n o t p _ e n temp160 temp160 temp160 ! temp160 s t a n d b y standby & sleep rw a k e_ w a it 128msec rwake ! por_vcc reset timeout t e m p s h u t d o w n ! por_vcc || wwdtimeout standby wait txwd_timeout temp160 ! s t a n d b y t e m p s h u t d o w n txwd wait tx=1 t e m p s h u t d o w n temp160 temp160 ! por_vcc r x = 0 rwake temp160 ! por_vcc || wwdtimeout
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 20 - 34 as8520 preliminary data sheet - application information 8 application information 8.1 initialization when the power supply is switched on, if vsup > vsuvr_off, reset_vsup_n becomes inac tive (high). after this, the voltage regula tor starts with a default ldo output setting of 3.3v and vuvr_off setting of 2.75v. if v cc > vuvr_off (2.75v), active-low porn_2_otp is generated. the rising edge of porn_2_otp loads contents of fuse onto the otp latch after load access time t load . load_otp_in_prereg signal loads contents of otp latch onto the pre-regulator domain register. th is register gives actual settings of ldo, vuvr_off and reset ti meout period t res . this is done because the otp block is powered by the v cc . if v cc > vuvr_off (phase 2), reset timeout is restarted. reset signal is de- asserted after reset timeout period t res (phase 2) and then device enters into normal mode. the circuit also needs to initialize correctly for very slow ramp rates on vsup (of the order of 0.5v/min). figure 7. initialization sequence for as8520 table 15. vsup>vsuvr_on and v cc www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 21 - 34 as8520 preliminary data sheet - application information 8.2 wake-up if the regulator is put into sleep/standby mode, it can be woken up with the bus interface. a transition on the bus (high to lo w) with a minimum predefined low time (t wake ) puts the regulator into normal mode. 8.3 over-temperature shutdown if the junction temperature increases beyond t sd the over-temperature recognition will be activated and the regulator voltage will be switched off. the v cc voltage drops down, the reset state is entered and the bus transceiver is switched off (recessive state). after t j falls below t ret , the as8520 will be initialized again. this initialization starts independently from the voltage levels on en and bus. within the th ermal shutdown mode, the transceiver cannot switch to the normal mode either with local or with remote wake-up. the operation of the as8520 is possible between t j (125oc) and the switch off temperature t sd , but small parameter differences can appear. after over-temperature switch-off, the ic initializes as explained in initialization on page 20 . the low slew mode for lin transceiver has to be selected again on re-initialization, if necessary. 8.4 lin bus transceiver the as8520 has an integrated bi-directional bus interface device for data transfer between lin bus and the lin protocol control ler. the transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver with high voltage c omparator followed by a de-bouncing unit. 8.4.1 transmit mode during transmission the data at the pin tx will be transferred to the bus driver to generate a bus signal. to minimize the elec tromagnetic emission of the bus line, the bus driver has an integrated slew rate control and wave shaping unit. transmitting will be interrupted in the following cases: sleep mode thermal shutdown active master reset (vsup < vsuvr_on) the recessive bus level is generated from the integrated 30k pull up resistor in serial with an active diode this diode prevent s the reverse current of vbus during differential voltage between vsup and bus (vbus>vsup). no additional termination resistor is necessary t o use the as8520 in lin slave nodes. if this ic is used for lin master nodes it is necessary that the bus pin is terminated via an extern al 1k resistor in series with a diode to vbat. 8.4.2 receive mode the data signals from the bus pin will be transferred continuously to the pin rx. short spikes on the bus signal are suppressed by the implemented de-bouncing circuit. including all tolerances the lin specific receive threshold values of 0.4*vsup and 0.6*vsup wi ll be securely observed. reset = disabled reset = high-z resistive divider = disabled vbat = high, vbat_div = low table 16. vsup www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 22 - 34 as8520 preliminary data sheet - application information figure 8. receive mode impulse diagram 8.5 rx and tx interface 8.5.1 input tx the 5v input tx controls directly the bus level. lin transmitter acts like a slew-controlled level shifter. a dominant state (l ow) on tx leads to the lin bus being pulled low (dominant state) too. the tx pin has an internal active pull up connected to v cc . this guarantees that an open tx pin generates a recessive bus level. figure 9. tx input circuitry 8.5.2 output rx the received bus signal will be output to the rx pin: bus < vthr_cnt ? 0.5 * vthr_hys rx = low bus > vthr_cnt + 0.5 * vthr_hys rx = high this output is a push-pull driver between v cc and gnd with an output current of 1ma. rx bus t < t deb_bus t < t deb_bus 50% 60% 40% v thr_cnt v thr_max v thr_min v thr_hys as8520 vcc mcu rc-filter (10ns) vcc i pu_txd tx
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 23 - 34 as8520 preliminary data sheet - application information figure 10. rx output circuitry 8.6 mode input en the as8520 is switched from normal mode to the standby/sleep mode with a falling edge on en and keeping tx high for t stndy_trigger time. device is switched from standby mode to normal mode with a rising edge at the en pin. the mode change for as8520 with a falling edge at en can be done independently from the state of the bus transceiver. device enters into serial port mode (for factory test purpose only) by forcing en low and driving tx high to low within t tx_sp_trigger time after en forced to low. this ensures the direct control of device to enter into standby/sleep mode by microcontroller using en pin. figure 11. en pin functionality the en input has an internal active pull down to secure that if this pin is not connected, a low level will be generated. mcu as8520 vcc rx en tx rd wr len1 len0 a4 d3 d2 d1 d0 normal mode normal mode serial port mode normal mode standby/sleep mode entry into serial port mode t tx_su t tx_hd t tx_su t tx_sp_trigger t stndy_trigger t en_ensclk
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 24 - 34 as8520 preliminary data sheet - application information figure 12. enable controlled via. mcu if the application doesn?t need the wake up capability of the as8520, a direct connection en to v cc is possible. in this case the as8520 operates in permanent normal mode. also possible is the external (outside of the module) control of the en line via. vsup signa l as shown below. figure 13. permanent normal mode en vsup vss ldrive1 vbat_div vcc reset rx tx ldrive2 sdi as8520 mcu + 5v c load v bat lin + vbat cs sdo sclk en vsup vss ldrive1 vbat_div vcc reset rx tx ldrive2 sdi as8520 mcu + 5v c load v bat lin + vbat cs sdo sclk
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 25 - 34 as8520 preliminary data sheet - application information 8.7 serial port interface the 4-wire interface is essentially used to control the relay driver, to shutdown ldo temporarily and to trigger the window wat chdog. it is also used to access test mode and read out diagnostic information for the as8520. the description of this interface and the protocol is explained below. information on block status and errors can be displayed by diagnosis registers. 8.7.1 device configuration using 4-wire serial port the spi interface can be used as interface between the as8520 and an external microcontroller to configure the device and acces s the status information. the interface is a slave and then only the microcontroller can start the communication. the spi protocol is very s imple and the length of each frame is an integer multiple of byte except when a transmission is started. basically each frame has 1 command b it, 5 address/ configuration bits, 1 or more data bytes. spi clock polarity settings depend on the value of the sclk on the cs falling edge. t his setting is done on each start of the spi transaction. during the transaction, th e spi clock polarity will be fixed to the settings done. on the cs falling edge, the values on sclk signal decide setting of the active spi clock edge for data transfer. (see table below) 8.7.1.1 spi frame a frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an int eger number of bytes. command is coded on the 1 first bit, while address is given on lsb 5 bits. (see table below) if the command is read or write, one or more bytes follow. wh en the micro-controller sends more bytes (keeping cs low and sclk toggling), the spi interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses. 8.7.1.2 write command for write command c0 = 0. after the command code c0 and two reserved bits, the address of register to be written has to be provided from the msb to the l sb. then one or more data bytes can be transferred, always from the msb to the lsb. for each data byte following the first one, used address is the incremented value of the previously written address. each bit of the frame has to be driven by the spi master on the spi clock transfer edge and the spi slave on the next spi clock edge samples it. these edges are selected as per table 17 . the following figures illustrate two examples of write command (without and with address self-increment.) table 17. cs and sclk cs sclk description fall low serial data transferred on rising edge of spi clock. sampled at falling edge of spi clock. fall high serial data transferred on falling edge of spi clock. sampled at rising edge of spi clock. any any serial data transfer edge is unchanged. table 18. command bits command bits register address or transmission configuration c0 reserved reserved a4 a3 a2 a1 a0 c0 command description 0 write address writes data byte on the given starting address. 1 read address read data byte from the given starting address.
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 26 - 34 as8520 preliminary data sheet - application information figure 14. protocol for serial data write with length = 1 figure 15. protocol for serial data write with length = 4 8.7.1.3 read command for read command c0 = 1. after the command code c0 and two reserved bits, the address of register to be read has to be provided from the msb to the lsb. then one or more data bytes can be transferred from the spi slave to the master , always from the msb to the lsb. to transfer more bytes fro m consecutive addresses, spi master has to keep active the spi cs signal and the spi clock as long as it desires to read data from the slave. each bit of the command and address sections of the frame have to be driven by the spi master on the spi clock transfer edge and the spi slave on the next spi clock edge samples it. each bit of the data section of the frame has to be driven by the spi slave on the spi clock transfe r edge and the spi master on the next spi clock edge samples it. these edges are selected as per table 17 . the following figures illustrate two examples of read command (without and with address self-increment.) cs sclk sdi sdo 0 res1 res0 a4 a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d7 d6 transfer edge sampling edge data d7 ? d0 is moved to address a4..a0 here cs sclk sdi sdo 0 r es 1 a 1 a 4 a 2 a 3 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 data d7-d0 is moved to address a4-a0 here data d7-d0 is moved to address a4-a0 +1 here data d7-d0 is moved to address a4-a0 +2 here data d7-d0 is moved to address a4-a0 +3 here data d7-d0 is moved to address a4-a0 +4 here a 0 r es 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 27 - 34 as8520 preliminary data sheet - application information figure 16. protocol for serial data read with length = 1 figure 17. protocol for serial data read with length = 4 cs sclk sdi sdo 1 res1 res0 a4 a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d7 d6 transfer edge sampling edge data d7 ? d0 at address a4..a0 is read here transfer edge sampling edge cs sclk sdi sdo 1 r e s1 r e s0 a 4 a 0 a 1 a 2 a 3 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 data d7-d0 at address a4-a0 is read here data d7-d0 at address a4-a0 +1 is read here data d7-d0 at address a4-a0 +2 is read here data d7-d0 at address a4-a0 +3 is read here data d7-d0 at address a4-a0 +4 is read here
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 28 - 34 as8520 preliminary data sheet - application information 8.7.1.4 timing the following figures illustrate timing waveforms and parameters. figure 18. timing for writing figure 19. timing for reading cs sdi sdo sclk ... ... ... t cps t cphd t dis t dih clk polarity datai datai datai ... t csh t sclkh t sclkl cs sclk sdi sdo t dohz t dod datai datai datao (d7 n ) datao (d0 0 ) t sclkh t sclkl
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 29 - 34 as8520 preliminary data sheet - application information 8.8 control and diagnosis registers the serial interface can be used as interface between the assp as 8520 and an external micro-controller. the interface is a slav e and only the micro-controller can start the communication. this interface will be used for device configuration, entering into test mode and carrying out diagnostic options. refer to table 19 for details on the configuration registers. 8.8.1 definition of cont rol and status registers a total of 32 control, diagnosis and test registers, each of 8-bit can be accessed using the 4-wire serial interface. table 19 provides a description of all control and status registers. table 19. configuration registers addr register name por value bit type description control and configuration register 0 x 02 otp interface control register on por_vcc 0000_0000 b[7:1] r/w reserved b[0] otp feature is only for factory use! 0 otp interface is disabled. 1 otp interface is enabled. when this bit is set, en, tx, rx are used as otp interface pads. these pads can be used for otp programming. otp interface is disabled on seeing high to low transition on rx (mode). 0 x 03 device configuration register on por_vcc 0000_1011 b[7:4] r/w reserved b[3] 0 lin transceiver disabled 1 lin transceiver enabled b[2] 0 over-temperature monitor disabled 1 over-temperature monitor enabled b[1] 0 low side driver2 disabled 1 low side driver2 enabled b[0] 0 low side driver1 disabled 1 low side driver1 enabled 0 x 04 device control register on por_vsup 0000_0001 b[7:1] r/w reserved b[0] slew control 0 low slew mode 1 high slew mode 0 x 05 temporary shutdown register on por_vcc 0000_0000 b[7:1] r/w reserved b[0] temporary shutdown control bit 0 no temporary shutdown 1 enter into temporary shutdown 0 x 06 window watch dog trigger register on por_vcc 0000_0000 b[7:1] w reserved b[0] window watch dog trigger. this bit will be set by mcu to indicate trigger event. if this trigger occurs outside the window of watchdog counter, then reset signal is asserted. also on this trigger wwd counter is restarted and this bit will be cleared internally within 2 cycles of 128khz clock. 0 x 07 low side driver data register on por_vcc 0000_0000 b[7:2] r/w reserved b[1] this bit is data input to low side driver 2 gate input b[0] this bit is data input to low side driver 1 gate input
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 30 - 34 as8520 preliminary data sheet - application information diagnosis register 0 x 08 diagnostic register 1 on por_vsup 0000_001 r b[7:0] are 8 lsb bits of the 24 bit diagnostic register b[7] wwdt window watchdog timeout (set on failure of window watchdog timeout, cleared after c read b[6] rwake remote wakeup (set on remote wa keup event on lin bus, cleared after c read) b[5] reserved b[4] ovvbat overvoltage vbat (set when vsup > vovthh, cleared after c read) b[3] otemp140 over-tempe rature warning (set when temp > totset, cleared after c read) b[2] otemp160 over-temperature reset (set when temp > tsd, cleared after c read) b[1] uvvcc undervoltage v cc (set when v cc < vuvr_on, cleared after c read) b[0] porvsup (set when vsup < vsuv r_on, cleared after c read) 0 x 09 diagnostic register 2 on por_vsup 0000_0000 r b[7:0] = dr[15:8] next 8 lsb bits of the 24 bit diagnostic register. b[7:2] reserved b[1] tempshut this bit is set on entering into temporary shutdown state and cleared after c read. b[0] txtimeout tx timeout of 1sec (set on tx low > 1sec, cleared after c read) 0 x 0a reserved 0 x 0b reserved 0 x 0c reserved 0 x 0d reserved 0 x 0e reserved 0 x 0f reserved 0 x 10 backup register 1 on por_vsup 0000_0000 b[7:0] r/w this can be used to store configuration/status data during sleep mode. 0 x 11 backup register 2 on por_vsup 0000_0000 b[7:0] r/w this can be used to store configuration/status data during sleep mode. 0 x 12 backup register 3 on por_vsup 0000_0000 b[7:0] r/w this can be used to store configuration/status data during sleep mode. 0 x 13 backup register 4 on por_vsup 0000_0000 b[7:0] r/w this can be used to store configuration/status data during sleep mode. 0 x 14 backup register 5 on por_vsup 0000_0000 b[7:0] r/w this can be used to store configuration/status data during sleep mode. 0 x 15 backup register 6 on por_vsup 0000_0000 b[7:0] r/w this can be used to store configuration/status data during sleep mode. table 19. configuration registers addr register name por value bit type description
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 31 - 34 as8520 preliminary data sheet - application information 8.9 esd/emc remarks 8.9.1 general remarks electronic semiconductor products are sensitive to electro static discharge (esd). always observe electro static discharge cont rol procedures whenever handling semiconductor products. 8.9.2 esd-test the as8520 is tested according cdf-aec-q100-002 / mil883-3015. 7 (human body model), iec 61000-4-2, jesd22-c101/ aec-q100-011, jesd22-a115/aec-q100-003. 8.9.3 emc the test on emc impacts is done according to iso 7637-1 for power supply pins and iso 7637-3 for data and signal pins. 0 x 16 backup register 7 on por_vsup 0000_0000 b[7:0] r/w this can be used to store configuration/status data during sleep mode. 0 x 17 backup register 8 on por_vsup 0000_0000 b[7:0] r/w this can be used to store configuration/status data during sleep mode. table 19. configuration registers addr register name por value bit type description
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 32 - 34 as8520 preliminary data sheet - pack age drawings and markings 9 package drawings and markings the device is available in a 24-pin qfn (6x6) package. figure 20. package drawings table 20. package dimensions symbol mm min typ max d6 e6 d1 4.40 4.50 4.60 e1 4.4 4.50 4.60 l 0.35 0.40 0.45 b 0.25 0.30 0.35 e0.65 a 0.80 0.85 0.9 a1 0.203 aywwizz as8520 51111y 19 24 6 1 12 7 13 18
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 33 - 34 as8520 preliminary data sheet - revision history revision history table 21. revision history revision date owner description
www.austriamicrosystems.com/lin_companionic/as8520 revision 0.01 34 - 34 as8520 preliminary data sheet - ordering information 10 ordering information the devices are available as the standard products shown in table 22 . note: all products are rohs compliant and pb-free. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicros ystems.com/distributor copyrights copyright ? 1997-2009, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the st andard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact table 22. ordering information ordering code description delivery form package AS8520-AQFT v cc = 5v tape & reel 24-pin qfn (6x6)

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